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Cache and Multiprocessing

Introduction

Modern CPUs run far faster than DRAM. Cache memory hides that gap by keeping copies of recently used data close to the core. Multiprocessing adds cores or threads to increase throughput — but shared caches, buses, and memory create coherency and contention problems. Embedded SoCs (dual-core M7+M4, quad Cortex-A) require you to know when cache matters for DMA and why two tasks on two cores still fight over one SDRAM bus.

Memory hierarchy

Level Typical size Speed Managed by
Registers tens Fastest Compiler
L1 cache 16–64 KB per core ~1–4 cycles Hardware
L2 cache 128 KB–1 MB tens of cycles Hardware
L3 cache MB scale (shared) slower Hardware
RAM MB–GB hundreds of cycles Software
Storage flash/SSD ms Software

Principle of locality: programs reuse the same data (temporal) and nearby addresses (spatial) soon after access — caches exploit this.

Cache operation

On read miss, hardware fetches a cache line (often 32 or 64 bytes) from RAM into cache. On write, policies differ:

Policy Behaviour
Write-through Every write goes to RAM immediately — simple, slower
Write-back Write to cache; flush line to RAM when evicted — faster, coherency care

Hit rate drives performance — profiling tools (perf, ARM DS-5) show miss rates.

Cache types (mapping)

Type Mapping Trade-off
Direct-mapped One RAM block → one cache line slot Conflicts if two hot addresses alias
Fully associative Any line anywhere Expensive comparators
Set-associative N ways per set — common compromise 4-way, 8-way typical

You rarely configure this in software — but alignment and stride in loops affect conflict misses.

Cache and DMA (embedded critical)

When DMA writes to RAM, CPU cache may hold stale copies:

Architecture Typical fix
Cortex-M (no cache) Often none — still use volatile and barriers
Cortex-A with cache Clean/invalidate cache lines around DMA buffer
Hardware coherency Some SoCs snoop DMA — read TRM

Rule: DMA buffers often need alignment to cache line size and explicit cache maintenance in driver.

Flynn's taxonomy

Classifies parallel computers by instruction and data streams:

Class Instructions Data Example
SISD Single Single Classic single-core MCU
SIMD Single Multiple ARM NEON, DSP vector ops
MISD Multiple Single Rare (fault tolerance)
MIMD Multiple Multiple Multi-core CPU, multi-MCU

SIMD: one instruction adds 4 floats at once — use for DSP when library supports it.
MIMD: independent cores run different tasks — FreeRTOS SMP, Linux on quad-A53.

flowchart LR subgraph simd [SIMD] ONE1[One instruction] --> D1[Data lane 1] ONE1 --> D2[Data lane 2] ONE1 --> D3[Data lane 3] end subgraph mimd [MIMD] C1[Core 1 program] C2[Core 2 program] end

Multiprocessing models

Model Description
Symmetric (SMP) All cores equal — run any task
Asymmetric (AMP) Core 0 runs Linux, core 1 runs bare-metal RTOS
Hardware threads (SMT) Hyper-threading — rare on embedded

AMP on one chip: OpenAMP, RPMsg for inter-core messaging — common in NXP i.MX, STM32MP1.

Synchronization on shared memory

Primitive Use
Mutex Exclusive access
Spinlock Short critical sections on SMP
Atomic operations Lock-free counters
Memory barrier Ordering visible to other cores

False sharing: two cores update different variables in same cache line — causes unnecessary coherency traffic. Pad structures to cache line boundaries in hot paths.

When multiprocessing helps embedded

Helps Hurts
Separate networking stack from control loop Single SDRAM bus bottleneck
Vision on core A, motor on core B Debug complexity
Linux + RTOS split Shared resource locking bugs

Profile before adding cores — a faster single-threaded loop may beat two contended cores.

Relevant topics

Starting points

  1. Run perf stat on Linux SBC for cache-miss vs hit-heavy loops.
  2. Align DMA buffer to 32 bytes — compare behaviour with misaligned buffer on Cortex-A.
  3. Map which core runs which task on dual-core MCU example project.
  4. Read ARM cache maintenance chapter before writing a DMA driver.

Focus points

  • Cache invisible on many MCUs — still know DMA coherency on application processors.
  • Volatile ≠ cache-safe for DMA — need explicit invalidate/clean.
  • Lock contention scales badly — prefer message passing between cores.
  • SIMD needs aligned data — check compiler flags and intrinsics.

Key points

  • Caches exploit locality to bridge CPU–RAM speed gap; write-back is common.
  • DMA + cache requires clean/invalidate discipline on cached systems.
  • Flynn's taxonomy: SISD, SIMD, MISD, MIMD classify parallel hardware.
  • SMP vs AMP — choose how cores share work in multi-core embedded SoCs.