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BoKSA

Hardware

Computer Architecture

Introduction

Computer architecture describes how CPU, memory, and I/O connect and cooperate: instruction formats, buses, interrupt handling, and design trade-offs between von Neumann and Harvard models. For embedded work, architecture explains why flash wait states matter, why separate instruction and data buses exist on DSPs, and how exceptions replace polling.

This article bridges fundamentals and hardware implementation — aligned with buses, Harvard architecture, and system structure.

von Neumann architecture

Single memory holds both instructions and data. CPU fetches over a shared bus.

Advantage Disadvantage
Simple, flexible von Neumann bottleneck — one bus for fetch and data
Easy to load programs Security: data can be executed if not protected

Most desktop and server CPUs are von Neumann at the logical level (with caches hiding physical details).

flowchart TB CPU[CPU] MEM[(Unified memory)] IO[I/O devices] CPU <-->|Shared bus| MEM CPU <-->|I/O bus| IO

Harvard architecture

Separate instruction and data memories (and often buses):

Advantage Disadvantage
Fetch instruction and data in parallel Two memory interfaces — more pins, complexity
Predictable timing for DSP/MCU Loading programs requires special paths

Many MCUs use Harvard internally (flash for code, SRAM for data) while exposing a unified address space to the programmer via the bus matrix.

Buses

A bus is a shared set of lines for address, data, and control.

Signal group Role
Address Which memory location or device
Data Bits read or written
Control Read/write, clock, ready, chip select

Bus width

  • 8-bit bus — one byte per transfer; cheaper, slower for bulk data.
  • 32-bit bus — common on ARM Cortex-M; matches register width.
  • 64-bit — servers and high-end application processors.

Wider buses move more per clock but need more pins and PCB routing.

Exceptions and interrupts

Instead of polling a button forever, hardware signals the CPU via interrupt:

  1. Current context saved (partially — handler does the rest).
  2. Interrupt service routine (ISR) runs.
  3. Execution resumes where it left off.
Term Meaning
IRQ Interrupt request line
Vector table Addresses of handler entry points
Nested interrupts Higher priority can preempt lower
Exception Interrupt + faults (hard fault, undefined instruction)

Latency = time from event to first instruction in ISR — critical for real-time (see Real-time systems).

Pipelining (concept)

CPUs overlap fetch, decode, execute stages:

1
2
3
Instr 1: [F][D][E]
Instr 2:    [F][D][E]
Instr 3:       [F][D][E]

Branches and dependencies cause stalls and flushes — why tight loops and predictable branches run faster.

Embedded-specific notes

Topic Practical impact
Memory-mapped I/O GPIO at fixed addresses — no special I/O instructions
Bit-banding (some ARM) Atomic single-bit writes to memory
MPU Memory Protection Unit — optional regions for safety
FPU Hardware float — check __FPU_PRESENT
Thumb / Thumb-2 Compact 16/32-bit instruction mix on Cortex-M

Relevant topics

Starting points

  1. Read your MCU reference manual "System architecture" chapter — sketch buses.
  2. List all interrupt sources in your project and their priorities.
  3. Measure interrupt latency with GPIO toggle at ISR entry.
  4. Compare flash vs RAM execution speed on your board.

Focus points

  • Harvard vs von Neumann explains parallel fetch and MCU memory layout.
  • Bus width and clock bound throughput — not just CPU MHz.
  • ISRs must be short — defer work to main loop or RTOS tasks.
  • Vector table must be correct at boot — bootloader updates need care.

Key points

  • von Neumann: unified memory; Harvard: separate instruction and data paths.
  • Buses carry address, data, and control between CPU, memory, and I/O.
  • Interrupts/exceptions enable reactive, efficient I/O handling.
  • Embedded MCUs combine architectural ideas with memory-mapped peripherals and optional MPU/FPU.