Sequential Logic Design

Introduction

Combinational logic outputs depend only on current inputs. Sequential logic adds memory: outputs depend on past inputs through stored state. Flip-flops, counters, and state machines power everything from UART baud generators to motor controllers and industrial PLCs.

This article covers latches and flip-flops, counters, finite state machines (FSMs), and Karnaugh maps for minimizing logic — the design tools you use when firmware alone is too slow or you need hardware-accurate timing.

Latches vs flip-flops

D flip-flop

On clock edge, output Q takes input D. Used to build registers and shift registers.

JK flip-flop

Toggles when J=K=1; holds when J=K=0; sets/clears when only one is 1. General-purpose but D flip-flops dominate modern designs.

Synchronous design

Global clock drives all flip-flops on the same edge:

Rules:

1. One clock domain per simple design (or use synchronizers when crossing domains).
2. Avoid asynchronous inputs without metastability handling.
3. Register outputs before long combinational paths (pipeline).

Counters

MCU hardware timers are sophisticated counters with prescalers, compare registers, and PWM — prefer them over bit-banging when accuracy matters.

Finite state machines (FSM)

An FSM has:

• States — e.g. IDLE, SENDING, WAIT_ACK
• Inputs — events, sensor flags
• Outputs — motor on, LED, next state
• Transitions — rules from (state, input) → next state

Moore vs Mealy

Document FSMs with state diagrams and transition tables — same skill for HDL, PLC ladder logic, and firmware switch(state).

Example: simple UART transmitter (conceptual)

See Serial communication protocols.

Karnaugh maps (K-maps)

K-maps visually minimize Boolean expressions for 2–4 variables (sometimes more).

Steps:

1. Build truth table from specification.
2. Place 1s in K-map grid (Gray code column/row order).
3. Circle largest groups of 2, 4, 8 cells (powers of two).
4. Read off product-of-sums or sum-of-products terms.

Example benefit: A 4-variable function might reduce from 6 product terms to 3 — fewer gates, lower power.

For more variables, use Quine–McCluskey or let synthesis tools optimize — but K-maps build intuition.

Hazards and glitches

Static hazard: output glitches 0→1→0 during input change.
Fix: add redundant terms from K-map adjacency, or register outputs.

In firmware state machines, equivalent issues appear as race conditions — use clear state entry/exit and atomic updates.

Relevant topics

• Digital logic fundamentals
• PLCs and industrial control
• Firmware architecture
• Karnaugh map (Wikipedia)
• Finite-state machine

Starting points

1. Draw a 3-state FSM for a pedestrian crossing light (red/yellow/green).
2. Minimize a 3-variable function with a K-map on paper.
3. Configure an MCU timer as a modulo-1000 counter — compare to ripple counter concept.
4. Refactor messy if chains in firmware into an explicit enum state machine.

Focus points

• Edge-triggered flip-flops are the basis of reliable synchronous design.
• FSM diagrams should be drawn before coding — for MCU, FPGA, or PLC.
• K-maps teach minimization; tools finish the job at scale.
• Metastability when crossing clock domains — use 2+ flip-flop synchronizers.

Key points

• Sequential logic stores state; outputs depend on history, not just current inputs.
• Counters and shift registers are built from flip-flops.
• FSMs model control behaviour — Moore vs Mealy trade timing vs structure.
• Karnaugh maps minimize combinational logic for small variable counts.